Tutorial Sessions

IEEE Space, Aerospace and Defence Conference, SPACE 2025

Next-Gen Verification Strategies for Complex SoCs: AI-Driven, Scalable, and Future-Ready

The complexity of today’s SoCs is unprecedented multi-core architectures, AI/ML accelerators, safety-critical functionality, and tightly integrated heterogeneous blocks have pushed traditional verification methodologies to their limits. With verification now consuming over 70% of the design lifecycle, the industry is at an inflection point: we must move beyond legacy flows and adopt intelligent, scalable strategies that deliver both speed and confidence. This Presentation is a forward-looking view of next-generation verification strategies, rooted in real-world challenges and practical innovation. We’ll explore how to shift verification earlier in the lifecycle with robust pre-silicon planning, drive coverage closure across fragmented domains, and ensure readiness for power, performance, and safety compliance. A strong emphasis will be placed on how AI and ML are transforming the verification landscape from smarter test generation and regression analytics to predictive debug and automated root-cause analysis.

Key Topics Covered:

The Urgency for Next-Gen Verification
Shifting Verification Left
Coverage Closure in the Modern Era
Hybrid Verification Approaches
AI & ML in Verification Workflows
Future-Forward Verification Trends
Evolving the Verification Ecosystem

Despite the proven success of MHT as a methodology for MTT, computational constraints and other fundamental performance limitations may lead to unacceptable performance in some settings. We discuss the benefits that can be achieved with multi-stage MHT processing. In many settings, judicious distributed MHT processing enables improved performance over (necessarily suboptimal) centralized MHT. We provide illustrative examples from several domains. Additionally, we describe recent advances in graph-based tracking, a fast (approximate) approach to MHT that provides improved results in certain applications.

Bio-sketch for Speaker:

Sumit Kumar is a Senior Engineering Manager at Analog Devices India with over 1.4 decades of expertise in VLSI design verification and AI-driven methodologies. He holds a B.E from D.S.C.E and M.Tech from BITS Pilani and an Executive Management from IIM Bangalore.

He lead the entire front-end design and design verification for System-on-Chip (SoC) solutions, ensuring robust design verification methodologies and execution. Previously, he worked with Cadence and Broadcom, where he was responsible for handling front end activity and COE’s for complex SoCs and IPs, gaining hands-on experience with high-performance silicon environments. In addition to his professional role, he am actively involved in technical conferences , Panel discussions , speaker on semiconductor topics like SOC & IP design , Design verification, both functional & formal verification & validation , functional safety and Over all semiconductor domains . Also mentor in the semiconductor field for Btech/Mtech and Experienced folks. Serving as Advisory Board , Advisory Panel Offering career guidance to students for many institutes in India. he am a recognized mentor, speaker, and panelist in the semiconductor domain. he was panel chair of VLSID 2025 conference too, he actively contribute to industry conferences and academic outreach programs, and am passionate about driving the next wave of innovation in design verification through intelligent methodologies and scalable architectures.

Sumit currently leads the front-end design and design verification for System-on-Chip (SoC) solutions, ensuring the implementation of robust verification methodologies and seamless execution. Prior to Analog Devices, Sumit worked at Cadence and Broadcom, where he played a key role in handling front-end activities and Centers of Excellence (COEs) for complex SoCs and IPs, gaining hands-on experience with high-performance silicon environments.

Sumit has led several initiatives focused on AI-powered verification, guiding large-scale SoC projects to successful first-pass silicon validation. His extensive experience spans across pre-silicon verification, post-silicon validation, emulation, and hardware/software co-verification for complex multi-core systems.

In addition to his technical expertise, Sumit is an active speaker at industry conferences, panel discussions, and academic events, covering topics like SoC & IP design, design verification (functional and formal), validation, functional safety, and various aspects of the semiconductor domain. He also serves as a mentor to BTech/MTech students and industry professionals, offering career guidance through being part of Advisory Board , Advisory Panel Offering career guidance to students. With a passion for shaping the future of the semiconductor field Sumit actively contributes to the education and mentoring of the next generation of engineers.